FPGA implementation of an electronic lock Gabriele Guarnieri, student Electronics Engineering, exam of Applied Electronics University of Trieste

Project description

The project consists in a simple multi-user electronic lock. The circuit was designed using VHDL hardware description language and Xilinx ISE WebPACK software tools, and implemented on a XESS XSA-50 board, which mounts a Xilinx Spartan-II XC2S50 FPGA, a Xilinx XC9572XL CPLD and a 128KB Atmel AT49F001 Flash memory, besides other devices and interfaces. The code is entered on a keyboard, which was taken from an old telephone. The passwords are stored in the Flash memory, and can be added, changed or removed by means of a specific administrator password; the Flash memory also contains the FPGA programming file, so that the circuit is automatically configured when power is applied. Due to the educational purpose of the work, the circuit was not connected to a physical lock but it simply displays its state on a 7-segment LED. The device has an asynchronous reset mechanism which can be triggered manually by means of the pushbutton on the XSA board and is generated internally by the circuit itself.

File download

Click here to download a ZIP file containing the project. The archive contains the following:

• cpld (folder) – Xilinx ISE 6.0 project for the CPLD program
• keyb (folder) – Xilinx ISE 6.0 project for the FPGA program
• config.svf – CPLD bitfile
• keyb.bit – FPGA bitfile
• keyb.mcs – Flash programming file for the FPGA bitfile
• password.xes – Flash programming file for the administrator password
• keyb.pdf – Project documentation (in italian)