#include "inoutcfg.h"
#include <csl.h>
#include "regs.h"
#include "c6211dsk.h"
#include <c6x.h>
#include <csl_irq.h>
#include <csl_mcbsp.h>
#include <csl_timer.h>
#include <csl_edma.h>
#include <csl_cache.h>

extern InoutIsr ();
extern fir_asm_init ();
void mcbsp0_init();
void mcbsp0_write(int out_data);
int mcbsp0_read();
extern int codec();
void start_timer1();

#define FCPU     150000000        	/* CPU clock frequency */
#define SRATE    8000             	/* data sample rate (simulated w/timer  */
#define TPRD     (FCPU/(4*2*SRATE)) /* timer period, using the clock mode */

TIMER_Handle hTimer;   				/* Handle for the timer device */

#pragma DATA_SECTION(R_in, "mydata");	/* Place data in internal memory */
#pragma DATA_SECTION(h, "mydata");    	/* Place data in internal memory */
#pragma DATA_ALIGN (R_in,256)
#pragma DATA_ALIGN (h,256)
short R_in[128]; 	/* Input samples R_in[0] most recent, R_in[127] oldest. */
short h[]=       	/* Impulse response of FIR filter. */
{
	   -2,    10,    14,     7,    -7,   -17,   -13 ,    3,
       19,    21,     4,   -21,   -32,   -16,    18 ,   43,
	   34,    -8,   -51,   -56,   -11,    53,    81 ,   41,
	  -44,  -104,   -81,    19,   119,   129,    24 , -119,
     -178,   -88,    95,   222,   171,   -41,  -248 , -266,
	  -50,   244,   366,   181,  -195,  -457,  -353 ,   85,
	  522,   568,   109,  -540,  -831,  -424,   474 , 1163,
	  953,  -245, -1661, -2042,  -463,  2940,  6859 , 9469,
	 9469,  6859,  2940,  -463, -2042, -1661,  -245 ,  953,
	 1163,   474,  -424,  -831,  -540,   109,   568 ,  522,
       85,  -353,  -457,  -195,   181,   366,   244 ,  -50,
     -266,  -248,   -41,   171,   222,    95,   -88 , -178,
   	 -119,    24,   129,   119,    19,   -81,  -104 ,  -44,
       41,    81,    53,   -11,   -56,   -51,    -8 ,   34,
   	   43,    18,   -16,   -32,   -21,     4,    21 ,   19,
	    3,   -13,   -17,    -7,     7,    14,    10 ,   -2
};


void main(void)
{
 	mcbsp0_init();
 	codec();     				/* Initialise the codec */
 	start_timer1();
 
 	IRQ_enable(IRQ_EVT_TINT1);
 	IRQ_test(IRQ_EVT_TINT1);
    
	IRQ_nmiEnable();
 	IRQ_enable(IRQ_EVT_TINT1);	/* Enables the Timer interrupt */
	
	fir_asm_init();
 	IRQ_globalEnable();

	for(;;);
}


void mcbsp0_init()
{
    /* Set up McBSP0 */
	*(unsigned volatile int *)McBSP0_SPCR = 0;	/* Reset serial port */
  
    *(unsigned volatile int *)McBSP0_PCR = 0;  	/* Set pin control reg */
   
   	/* Set rx control reg. one 16 bit data/frame */
   	*(unsigned volatile int *)McBSP0_RCR = 0x10040;
   	
   	/* Set tx control reg. one 16 bit data/frame */
   	*(unsigned volatile int *)McBSP0_XCR = 0x10040;
   	
   	*(unsigned volatile int *)McBSP0_DXR = 0;
   	
   	/* Setup SP control reg */
   	*(unsigned volatile int *)McBSP0_SPCR = 0x12001;
}


void mcbsp0_write(int out_data)
{
  	int temp;

  	temp = *(unsigned volatile int *)McBSP0_SPCR & 0x20000;

  	while ( temp == 0)
  	{
  		temp = *(unsigned volatile int *)McBSP0_SPCR & 0x20000;
  	}

  	*(unsigned volatile int *)McBSP0_DXR = out_data;
}


int mcbsp0_read()
{
  	int temp;

  	temp = *(unsigned volatile int *)McBSP0_SPCR & 0x2;

  	while ( temp == 0)
  	{
    	temp = *(unsigned volatile int *)McBSP0_SPCR & 0x2;
  	}

  	temp = *(unsigned volatile int *)McBSP0_DRR;
  	return temp;
}


void start_timer1()
{
	/* Disable output of Timer 1 */
	*(unsigned volatile int *)TIMER1_CTRL = 0x000;
 
 	/* Map TINT event to CPU interrupt 8 */
	IRQ_map(IRQ_EVT_TINT1,8);
   
	/* Open a handle to the Timer */
	
	hTimer = TIMER_open(TIMER_DEV1, TIMER_OPEN_RESET);

   /* Setup the timer */
  	TIMER_configArgs(hTimer, 
    	TIMER_CTL_OF(0x000003c1), 
    	TIMER_PRD_OF(TPRD), 
    	TIMER_CNT_OF(0)
  	);   

	/* Enable the timer */
	TIMER_start(hTimer);  	
}
